Hardware simulation completion is about 80%, of which:
– SH2 90% (part of the onchip modules like BSC, UBC is not simulated, exception handling and DMA are not complete)
– SCU 70% (DMA needs to be rewritten, DSP is done but does not work at this time)
– SMPC 80% (do not support 2P, multi-plug Multitap and many other peripherals are not simulated)
– VDP1 90% (drawing command close to completion but need to rewrite, need more accurate timing (Timing), Double interlace not simulated)
– VDP2 90% (RBG0 part is not completed, RBG1, EXBG not simulated, Cycle pattern register part of the unfinished, Line color screen rotation is not simulated, coefficient data is not simulated)
– M68K 95% (requires more precise Timing, some states of the CPU are not simulated)
– SCSP 70% (DSP is not simulated, MD (Modulation data) is not complete, PG (Phase generator) has a more serious problem)
– CDB 70% (part of the command is not simulated, CD Drive status is not complete)
– Controller: currently only supports 1P Digital pad
– Expansion card: now supports all the capacity, including memory card, extended memory card, but the default is to use the 32Mbit expansion card, by editing cart.json to automatically choose to switch to the memory card or expansion memory card.
– About speed: At present the main CPU SH2 only interpreter without JIT, which is a slow reason, another reason is to synchronize the sacrifices made by each device.
VDP2 support JIT, with the button « 9 » can be dynamically switched at runtime C + + core and JIT core, you can get a substantial increase in speed, but the JIT core is not the current completion of the C + + core so high, color operations, windows, shadows, etc. have not yet completed
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